1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory.
2. Related Art
With recent improvement in integration and reduction in cost of nonvolatile semiconductor memory devices, a local trap MONOS memory having a virtual ground array for locally trapping charges has been proposed.
Due to the virtual ground array, the local trap MONOS memory is characterized in its operation through selection transistors. An arranging method or driving method of the selection transistors is therefore important for the local trap type MONOS memory.
Hereinafter, the structure and operation of a conventional nonvolatile semiconductor memory device will be described with reference to the accompanying drawings (e.g., see U.S. Pat. No. 5,963,465).
First, the structure of a conventional nonvolatile semiconductor memory device will be described with reference to FIGS. 13 through 17.
FIG. 13 is a cross-sectional view of MONOS memory cells.
As shown in FIG. 13, a plurality of bit line diffusion layers 2 are provided at intervals on a semiconductor substrate 1. A charge trap film (ONO (Oxide-Nitride-Oxide) insulating film) 3 and a gate electrode 4 are sequentially formed over the semiconductor substrate 1 between the bit line diffusion layers 2. A bit line insulating film 10 is formed on the bit line diffusion layers 2. Note that the gate electrode 4 is formed also on the bit line insulating film 10 and extends in X direction (the left-right direction in the figure). The bit line diffusion layers 2 extend in Y direction (the direction vertical to the plane of the figure).
FIG. 14 is a circuit diagram of a memory array.
As shown in FIG. 14, selection transistors 6 are provided above and below memory cells 5. Each memory cell 5 have its gate electrode 4 connected to a corresponding memory word line (WL0, WL1) extending in X direction (the left-right direction in the figure). Although about 64 to 512 memory word lines are typically provided in Y direction (the up-down direction in the figure) between the selection transistors 6, only two memory word lines (WL0, WL1) are shown herein for convenience of explanation. Each selection transistor 6 is a transistor having a typical MOS structure and is formed by the gate electrode 4 common to the memory cells 5, a gate insulating film specific to the selection transistors 6, a source, a drain, and the like. Note that the gate electrode 4 of the selection transistors may be made of a different material from that of the gate electrode 4 of the memory cells 5.
A total of eight selection transistors 6 are provided above and below eight memory cells 5 arranged in X direction. The gate electrode 4 of each selection transistor 6 is connected to a corresponding one of selection word lines (SL-0 to SL-7) extending in X direction. A main bit line (MBL-0 to MBL-15) extending in Y direction is provided for every two memory cells 5 arranged in X direction, and is connected to the drain shared by two selection transistors 6. Note that, although about 1K main bit lines are typically provided in X direction, only 16 main bit lines (MBL-0 to MBL-15) are shown herein for convenience of explanation. Although FIG. 14 does not show connection between the main bit lines (MBL-0 to MBL-15) and the selection transistors 6, this connection is shown in FIG. 15 described below.
FIG. 15 is a partial enlarged view of FIG. 14 and shows connection between the main bit lines (MBL-0 to MBL-15) and the selection transistors 6.
As shown in FIG. 15, each main bit line is connected to the drain common to two selection transistors 6 and is connected to the bit line diffusion layers (source/drain) 2 (see FIG. 1) of the memory cells 5 through the selection transistors 6. Four main bit lines are thus provided for every eight memory cells 5 and are connected to eight bit line diffusion layers 2 through eight selection transistors 6.
FIG. 16 is an enlarged view of the array portion of the memory cells 5 shown in FIG. 14.
As shown in FIG. 16, the gate electrode of each memory cell 5 is connected to a corresponding one of memory word lines (WL0 to WL6) extending in X direction (the left-right direction in the figure), and the bit line diffusion layers 2 serving as the sources and drains of the memory cells 5 extend in Y direction (the up-down direction in the figure) to form diffusion layer bit lines (DBL-0 to DBL-20). Note that, in FIG. 16, twenty memory cells 5 are arranged in X direction and seven memory cells 5 are arranged in Y direction. Such a structure is arranged in a matrix pattern to form an array.
FIG. 17 shows a planar layout corresponding to the circuit diagram of the memory cell shown in FIG. 14. Note that FIG. 17 shows a half of the structure in the left-right direction in FIG. 14. In other words, FIG. 17 shows a region corresponding to the selection word lines (SL-0 to SL-7) and the main bit lines (MBL-0 to MBL-7).
As shown in FIG. 17, memory cells 5 formed by an active region (thin film region) 7, the bit line diffusion layers 2, and the gate electrode 4 are arranged in the left-right direction in the figure in a central region of the up-down direction in the figure. The selection transistors 6 formed by the active region 7 and the gate electrode 4 are provided above and below the memory cells 5. Each main bit line is connected to the active region 7 (drain) common to two selection transistors 6 through an MBL contact 9.
Hereinafter, operation of the conventional nonvolatile semiconductor memory device will be described with reference to FIGS. 18 through 24.
FIG. 18 shows a circuit diagram of write operation, and FIG. 19 is a corresponding cross-sectional view of memory cells in write operation.
As shown in FIG. 18, +9 V is applied to the memory word line WL, +5 V is applied to the bit line diffusion layer 2 on the right side of the memory cell 5 (Cell-2), and 0 V is applied to the bit line diffusion layer 2 on the left side of the memory cell 5 (Cell-2). The other bit line diffusion layers 2 are in an open state. As shown in FIG. 19, electrons a are thus injected to the right end of the charge trap film 3 of the memory cell 5 (Cell-2).
FIG. 20 is a circuit diagram of erase operation, and FIG. 21 is a corresponding cross-sectional view of memory cells in erase operation.
As shown in FIG. 20, −5 V is applied to the memory word line WL and +5 V is applied to the bit line diffusion layer 2 on the right side of the memory cell 5 (Cell-2). The other bit line diffusion layers 2 are in an open state. As show in FIG. 21, holes b are thus injected to the right end of the charge trap film 3 of the memory cell 5 (Cell-2) and the left end of the charge trap film 3 of the memory cell 5 (Cell-3).
FIG. 22 is a circuit diagram of read operation, and FIG. 23 is a corresponding cross-sectional view of memory cells in read operation.
As shown in FIG. 22, +5 V is applied to the memory word line WL, 0 V is applied to the bit line diffusion layer 2 on the right side of the memory cell 5 (Cell-2), and +1 V is applied to the bit line diffusion layer 2 on the left side of the memory cell 5 (Cell-2). The other bit line diffusion layers 2 are in an open state. As show in FIG. 23, in the case where electrons a have been injected to the right end of the charge trap film 3 of the memory cell 5 (Cell-2), a threshold voltage increases and therefore a small current flows between the source and drain of the memory cell 5 (Cell-2). In the case where holes b have been injected to the right end of the charge trap film 3 of the memory cell 5 (Cell-2), on the other hand, the threshold voltage decreases and therefore a large current flows between the source and drain of the memory cell 5 (Cell-2). Whether the memory cell 5 is in a written state or an erased state can thus be determined by comparing the source-drain current of the memory cell 5.
In each memory cell 5, the respective charge states of the right and left ends of the charge trap film 3 can be independently controlled. Therefore, a 2-bit state can be stored in each memory cell.
FIG. 24 is a circuit operation diagram corresponding to FIG. 16, illustrating a read state including the selection transistors 6. FIG. 24 shows an example of reading the charge state at the right end of the charge trap film 3 in the fourth memory cell 5 from the left in the figure.
As shown in FIG. 24, in order to apply +1 V to the left bit line diffusion layer 2 of the fourth memory cell 5 from the left, +1 V is applied to the main bit line (MBL-3) and 5 V is applied to the selection word line (SL-1) to turn on the selection transistor 6 having the gate electrode 4 connected to the selection word line (SL-1). In this way, +1 V applied to the main bit line (MBL-3) is transmitted to the source of the turned-on selection transistor 6, and +1 V is transmitted to the bit line diffusion layer 2 on the left side of the fourth memory cell 5 from the left connected to the source of the turned-on selection transistor 6. Similarly, in order to apply 0 V to the bit line diffusion layer 2 on the right side of the fourth memory cell 5 from the left, 0 V is applied to the main bit line (MBL-0) and 5 V is applied to the selection word line (SL-5) to turn on the selection transistor having the gate electrode 4 connected to the selection word line (SL-5). In this way, 0 V applied to the main bit line (MBL-0) is transmitted to the source of the turned-on selection transistor 6, and 0 V is transmitted to the bit line diffusion layer 2 on the right side of the fourth memory cell 5 from the left connected to the source of the turned-on selection transistor 6.
The potential state of a plurality of bit line diffusion layers 2 can thus be controlled by varying an applied voltage to the four main bit lines and eight selection word lines.
In a nonvolatile memory, the unit of memory capacity that can be rewritten (hereinafter, rewrite unit) is limited by a user's request and the like. In general, a smaller rewrite unit is better for the user in terms of usability. However, the smaller the rewrite unit is, the larger the area of the memory array becomes.
Hereinafter, a conventional method for reducing the rewrite unit in a MONOS memory having a virtual ground array for locally trapping charges will be described with reference to the figures.
In a MONOS memory having a virtual ground array, not only the selected memory cell 5 (Cell-2) but adjacent memory cells 5 (Cell-0, 1, 3, 4, 5, etc.) connected to the same memory word line WL are turned on in the written state shown in FIG. 18. Therefore, although a write current is shown to flow only in the selected memory cell 5 (Cell-2) in FIG. 18, a small current actually flows also in the adjacent memory cells 5 (Cell-0, 1, 3, 4, 5, etc.) connected to the same memory word line WL. These non-selected memory cells 5 are therefore brought into a slightly written state (this is generally called a write disturb phenomenon).
If the memory cell group belongs to the same rewrite unit, for example, if the adjacent memory cells belong to the same write unit, this write disturb occurs one to several times. However, if the memory cells belong to different rewrite units, for example, if one memory cell belong to a unit to be written and an adjacent memory cell belongs to a unit in an erased state, the write disturb may occur about ten thousand to a hundred thousand times in the unit in the erased state, whereby the unit changes from the erased state to the written state. In other words, data is destroyed.
In order to prevent such a write disturb phenomenon from occurring in a memory cell group belonging to different rewrite units, a structure for electrically dividing a virtual ground array into rewrite units has been proposed (e.g., see U.S. Pat. No. 6,975,536).
FIG. 25 schematically shows a chip layout obtained by dividing a virtual ground array by using X decoders (a decoder for driving memory word lines WL).
As shown in FIG. 25, in this method, one X decoder and one Y decoder are required for every rewrite unit, thereby increasing the chip size. Note that division in Y direction can be performed based on the selection transistors.
FIG. 26 schematically shows a chip layout obtained by dividing a virtual ground array within a memory cell array.
As shown in FIG. 26, since an X decoder and a Y decoder can be shared by a plurality of rewrite units, increase in chip size can be suppressed.
Referring to FIGS. 25 and 26, four X decoders are required in FIG. 25, while only one in FIG. 26. Since the X decoder of FIG. 26 needs to drive a larger memory word line capacity, the X decoder of FIG. 26 is larger in size than the X decoder in FIG. 25. However, the total X decoder area is smaller in FIG. 26 than in FIG. 25. Since approximately the same Y decoders can be used in both FIGS. 25 and 26 and the number of X decoders is smaller in FIG. 26 than in FIG. 25, a required chip size is smaller in FIG. 26 than in FIG. 25.
More specifically, provided that the area of each memory array 1, 2, 3, 4 in FIG. 25 is 1.0, the area of each X decoder 1, 2, 3, 4 is 0.3, and the area of each Y decoder 1, 2, 3, 4 is 0.3 in FIG. 25, the memory chip area in FIG. 25 is 1×4+0.3×4+0.3×4=6.4. On the other hand, provided that the area of each memory array 1, 2, 3, 4 is 1.0, the area of the X decoder is 0.6, and the area of the Y decoder is 0.3 in FIG. 26, the memory chip area in FIG. 26 is 1×4+0.6+0.3×4=6.4. The memory chip area ratio of FIG. 25 to FIG. 26 is 4.9/6.4. It can therefore be found that the area of FIG. 26 is 77% smaller than that of FIG. 25.
FIG. 27 is a circuit diagram illustrating write operation in the virtual ground array divided within the memory cell array as shown in FIG. 26.
As shown in FIG. 27, memory cells 5 (Cell-13 to 15) belong to a different rewrite unit from that of memory cells 5 (Cell-16 to 17). Since the bit line diffusion layer 2 on the right side of the memory cell 5 (Cell-15) is electrically isolated from the bit line diffusion layer 2 on the left side of the memory cell 5 (Cell-16), the write disturb phenomenon does not occur.
FIG. 28 shows a memory array circuit diagram in the case where the virtual ground array is divided within the memory cell array. In order to perform electrical isolation as described with reference to FIG. 27, the memory cells 5 are divided into groups of 16 memory cells so that the memory cell groups are electrically isolated from each other by an element isolation region 8.
FIG. 29 is a cross-sectional view of memory cells corresponding to a part of the circuit diagram of FIG. 28.
As shown in FIG. 29, the element isolation region 8 described with reference to FIG. 28 is provided between adjacent bit line diffusion layers 2. Note that this element isolation region 8 may be provided under the charge trap film 3, and a dummy memory cell 5 that is not used as an actual storage region may be provided in the element isolation region 8 for stable processing or the like.
FIG. 30 is an enlarged view of an array portion of the memory cells 5 in the circuit diagram of FIG. 28.
As shown in FIG. 30, the element isolation region 8 is provided for every memory cell group consisting of 16 memory cells 5. The element isolation region 8 is formed by forming an element isolation groove by using, for example, a shallow trench isolation method, a LOCOS (local oxidation of silicon) method or the like, and embedding a silicon oxide film or the like in the element isolation groove.
As has been described above, the chip layout obtained by dividing the virtual ground array within the memory cell array avoids the write disturb phenomenon by forming the element isolation region, and suppresses increase in chip size.